Microprocessor Monitor. General Description. The MAX is a plug-in upgrade of the. Dallas DS A reset pulse of at least ms duration is supplied on. Also featured is a debounced manual reset.
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The MAX enhances circuit reliability in P systems by monitoring the power supply, monitoring the software execution, and providing a debounced manual reset input. Also featured is a debounced manual reset input that forces the reset outputs to their active states for a minimum of ms.
A digitally programmable watchdog timer monitors software execution and can be programmed for timeout settings of ms, ms, or 1. The MAX requires no external components. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Measured with outputs open. All voltages referenced to GND. Guaranteed by desing. PBRST must be held low for a minimum of 20ms to guarantee a reset. A debounced active-low input that ignores pulses less than 1ms in duration and is guaranteed to recognize inputs of 20ms or greater. Time Delay Set. Tolerance Input. Ground Reset Output Active High. See RST. Strobe Input.
Input for watchdog timer. The reset outputs will remain in their active states until VCC has been continuously in-tolerance for a minimum of ms the reset active time to allow the power supply and P to stabilize. The microprocessor must toggle the ST input within a set period as determined by TD to verify proper software execution.
If a hardware or software failure keeps ST from toggling within the minimum timeout period—ST is activated only by falling edges a high-to-low transition —the MAX reset outputs are forced to their active states for ms Figure 2. This typically initiates the microprocessor's power-up routine. If the interruption continues, new reset pulses are generated each timeout period until ST is strobed. The timeout period is determined by the TD input connection.
The software routine that strobes ST is critical. The code must be in a section of software that executes frequently enough so the time between toggles is less than the watchdog timeout period. If both modes do not execute correctly, the watchdog timer issues reset pulses. The debounced input ignores input pulses less than 1ms and is guaranteed to recognize pulses of 20ms or greater.
Pushbutton Reset Figure 2. Pushbutton Reset. The debounced PBRST input ignores input pulses less than 1ms and is guaranteed to recognize pulses of 20ms or greater. Figure 4. Power-Down Slew Rate Figure 6. Package Information For the latest package outline information, go to www.
No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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